25 radhard msi logic UT54ACS14/ut54acts14 radiation-hardened hex inverting schmitt triggers dec. 1, 2003 features ? 1.2 radiation-hardened cm os (acts14) and 0.6 crh cmos process (acs14) - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 14-pin dip (not available for the acs14) - 14-lead flatpack description the UT54ACS14 and the ut54ac ts14 are hex inverters. the circuits perform the boolean function y = a . the devices are characterized over full military temperature range of -55 c to +125 c. function table logic symbol pinouts 14-pin dip top view 14-lead flatpack top view logic diagram input output a y h l l h y1 y2 y3 y4 (1) a1 (5) a3 (11) a5 (13) a6 note: 1. logic symbol in accordance with ansi/ieee standard 91-1984 and iec publication 617-12. 1 (3) a2 (9) a4 (2) (10) (12) (4) (8) y5 y6 (6) a1 y1 a2 y2 a3 y3 v ss v dd a6 y6 a5 y5 a4 y4 114 213 312 411 510 69 78 v dd a6 y6 a5 y5 a4 y4 a1 y1 a2 y2 a3 y3 v ss 114 213 312 411 510 69 78 y4 y3 y1 y2 y6 y5 a4 a3 a1 a2 a6 a5
radhard msi logic 26 UT54ACS14/ut54acts14 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation expo sure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device . this is a stress rating only, functional operation of the device at these or any other cond itions beyond limits indicated in the operational sections is not reco mmended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 (acts14) 5.0e5 (acs14) rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
27 radhard msi logic UT54ACS14/ut54acts14 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c) symbol parameter condition min max unit v t+ schmitt trigger, positive going 1 threshold acts acs 2.25 .7v dd v v t- schmitt trigger, negative going 1 threshold acts acs 0.5 .3v dd v v h schmitt trigger, typical range of hysteresis 2 acts acs 0.3 0.6 0.9 1.5 v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd -0.25 v i os short-circuit output current 2,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.8 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a ? i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 3.1 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
radhard msi logic 28 UT54ACS14/ut54acts14 notes: 1. functional tests are conducted in accordance with mi l-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within t he above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per ou tput buffer) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured fo r initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all acts specifications are valid for radiation dose < 1e6 rads(si), and all acs specifications are valid for radiation dose < 5e5 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested. ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 1, -55 c < t c < +125 c) notes: 1. maximum allowable relative shift equals 50mv. 2. for the acts version, all specifi cations are valid for radiation dose < 1e6 rads(si). for the acs version, all sp ecifications are valid for radiation dose < 5e5 rads(si). symbol parameter minimum maximum unit t phl input to yn 2 14 ns t plh input to yn 2 13 ns
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